The present invention generally relates to level conversion for multiple-supply voltages for very large scale integration systems and, more particularly, to low voltage-level down conversion with very low voltage operation for on-chip test circuitry.
Prior art voltage level conversion, e.g., for a dual-supply voltage system, is commonly performed through a differential inverter circuit. The output response for such a circuit is generally limited by the driving capability of the output inverter, e.g., a MOSFET (metal-oxide semiconductor field effect transistor) used to drive the load. Achieving low voltage operation by increasing the output driver size to get more current drive typically does not solve the problem due to the fact that upsizing the driver increases the intrinsic and coupling capacitance MOSFET devices typically have considerable coupling capacitance between their gate and drain terminals. The high edge rate of rise (fall) of drain voltage may couple capacitively to the gate of the MOSFET via the Miller capacitance. The coupling can cause the gate voltage of the MOSFET to rise resulting in unintended or deleterious operation of the circuit. Thus, upsizing the driver to get more current drive may in fact lead to a degradation rather than an improvement in level conversion circuit performance.
For an on-chip test circuit, one objective is to convert an input signal, e.g., a test noise pulse, from a high supply voltage level to a lower supply voltage level. Due to the trade-off between current drive and intrinsic capacitance, however, prior art circuits have not been able to achieve a satisfactorily short rise time of the output signal at the lower supply voltage while producing the current drive required. To illustrate, FIG. 1 shows transient response for one example of a prior art level converter on graph 100 of voltage, shown in millivolts (m) on the ordinate, against time, shown in nanoseconds (n) on the abscissa. Graph 100 shows output pulse 102 for comparison on the same graph with input pulse 106. Input pulse 106 is a result of non-inverted input pulse 104. As can be seen in FIG. 1, output pulse 102 has a poor rise time, indicated generally at 108, so that the output pulse rise time 116 (succinctly, the time for voltage of output pulse 102 to go from 10 % to 90% of the full amplitude voltage level) occupies an unacceptably large portion of the pulse width 110 of input pulse 102. For example, as shown in FIG. 1, the rise time 116 is approximately 1.7 nanoseconds out of the entire pulse width 110 of approximately 2.2 nanoseconds. In addition, the Miller capacitance effect may produce an initial voltage drop 112, which may also be referred to as coupling effect. Such a voltage drop 112 is the opposite of desired circuit performance for the rising edge 114 (LOW to HIGH transition) of the input pulse 104 and adversely affects the long rise time 116.
As can be seen, there is a need for a low voltage level converter that converts an input signal from a high supply voltage level to a lower supply voltage level. There is also a need for a level down converter that overcomes the limitations of Miller capacitance to provide required current drive with significantly improved, i.e., shortened, rise time of the output pulse.